Actually I've toyed with the idea of a "Plan 9 from 8-bit space". It
would be a fun challenge, I think, and I'd be interested to find
exactly what compromises would be needed. It may even be less of a
challenge than writing drivers for the crap peripherals ARM SOCs always
seem to be burdened with, but what could you do with it when it was
done?
What would be possible is to build a general purpose
building block. Something like this:
- provide a tiny thread library
- provide 9p over USB|serial|UDP
- implement a simple 9p server framework & export a server
side interface where one can plug in sensor/actuator
specific routines and specify the FS layout via a string.
- implement a namespace convention for discovering
capabilities (for example a "help/" dir)
- it should be implementable as a verilog block some day!
may be not but imagining that keeps the design simple.
Actually it doesn't have to be 9p. It can be something
simpler.