[9fans] new arm port: teg2

[g***@plan9.bell-labs.com]

After you pull, you should see a new directory,
/sys/src/9/teg2. From the _announce file:

This is a preliminary Plan 9 port to the Compulab Trimslice,
containing a Tegra 2 SoC: a dual-core, (truly) dual-issue 1GHz
Cortex-A9 v7a-architecture ARM system, *and* it comes in a case. VFP
3 floating-point hardware is present, but 5l doesn't yet generate
those instructions. This is the first multiprocessor ARM port we've
done, and much of the code should be reusable in future ports. There
are still things to be done but it can run both processors and is
believed to have adequate kernel support for VFP 3 floating-point.

[John Floren]

Great! Graphics support at this point, or is it still in the cpu server stage?

john

Post by g***@plan9.bell-labs.com
After you pull, you should see a new directory,
This is a preliminary Plan 9 port to the Compulab Trimslice,
containing a Tegra 2 SoC: a dual-core, (truly) dual-issue 1GHz
Cortex-A9 v7a-architecture ARM system, *and* it comes in a case.  VFP
3 floating-point hardware is present, but 5l doesn't yet generate
those instructions.  This is the first multiprocessor ARM port we've
done, and much of the code should be reusable in future ports.  There
are still things to be done but it can run both processors and is
believed to have adequate kernel support for VFP 3 floating-point.

[Anthony Sorace]

Post by John Floren
Great! Graphics support at this point, or is it still in the cpu server stage?

The version on sources, at least, doesn't seem to drive video. There are
pretty good notes on what works and what doesn't in that directory, in
particular words and notes/*.

[Charles Forsyth]

I've got one of the devices and was going to check some 5[acl] changes
Geoff had merged in, merge in any others from the Go 5[acl],
and (more originally) change the fp emulator to use VFP instead of 7500
instructions, so VFP can be made the default.
And 5i, I suppose.

Post by g***@plan9.bell-labs.com
VFP
3 floating-point hardware is present, but 5l doesn't yet generate
those instructions.

[David Leimbach]

Fantastic!

Post by g***@plan9.bell-labs.com
After you pull, you should see a new directory,
This is a preliminary Plan 9 port to the Compulab Trimslice,
containing a Tegra 2 SoC: a dual-core, (truly) dual-issue 1GHz
Cortex-A9 v7a-architecture ARM system, *and* it comes in a case. VFP
3 floating-point hardware is present, but 5l doesn't yet generate
those instructions. This is the first multiprocessor ARM port we've
done, and much of the code should be reusable in future ports. There
are still things to be done but it can run both processors and is
believed to have adequate kernel support for VFP 3 floating-point.

[erik quanstrom]

Post by g***@plan9.bell-labs.com
After you pull, you should see a new directory,
This is a preliminary Plan 9 port to the Compulab Trimslice,
containing a Tegra 2 SoC: a dual-core, (truly) dual-issue 1GHz
Cortex-A9 v7a-architecture ARM system, *and* it comes in a case. VFP
3 floating-point hardware is present, but 5l doesn't yet generate
those instructions. This is the first multiprocessor ARM port we've
done, and much of the code should be reusable in future ports. There
are still things to be done but it can run both processors and is
believed to have adequate kernel support for VFP 3 floating-point.

excellent. i've just had time to look at the block diagram.
is there a jtag connector somewhere?

- erik

[hiro]

Cool. I have a toshiba ac100 with a tegra2. But without graphics I'll
just go on and use drawterm some more time :(

sent from by d-bus